1. Field of the Invention
The present invention relates to telecommunications. In particular, the present invention relates to a novel and improved system for transmitting internal messages in a local network.
2. Description of the Related Art
Fault tolerant local computer networks are used when high reliability is required. Typical examples are modern telecommunication networks where system downtime must be minimized in order to provide service of acceptable quality. A common way to implement fault tolerance is to use replicated elements in the networks. A network with replicated application processes is a network where each application process is simultaneously running in at least two separate computer units. Thus, if a computer unit running a given application process goes down for whatever reason, there's still at least one more computer unit running the same process.
Message synchronism is one possible way to implement a network with replicated elements. In other words, when a transmitting application process sends a message to a receiving application process, an identical copy of the message is sent to each replicated (or redundant) receiving process running in various computer units. Each replicating receiving process must receive an identical message and in identical order to maintain synchronization of messages. Message synchronism is sometimes also referred to as input synchronism.
A network with message synchronism can be implemented either by software or by hardware. When implemented by software, a special software layer is implemented on top of a standard messaging protocols or technologies such as Ethernet or IP (Internet Protocol, IP). However, software based messaging consumes a substantial amount of computing power and network bandwidth.
Another way to implement a network which takes care of the message synchronism is to use special proprietary hardware, typically a message bus. When a message is sent from one computer unit to another, it is replicated in the message bus hardware. The message bus acts as a serializing point and the message order is preserved.
A typical example of such a hardware based prior art implementation is illustrated in FIG. 1. The system comprises multiple sending computer units CPUs, each for running at least one sending application process for sending an internal message. Since the system in question implements fault tolerance with replicated elements, each message is sent to two or more recipients. The system further comprises multiple receiving computer units CPUr, each for running at least one receiving application process for receiving a sent internal message, at least two copies of each receiving application process residing in said receiving computer units.
The system further comprises one proprietary interface unit IF per one or more computer units for buffering and relaying messages sent to and from the corresponding computer unit. Each interface unit comprises a transmitting buffer TX for storing one or more message to be sent until processed by the internal bus, and a receiving buffer RX for storing one or more received messages until processed by the corresponding computer unit.
The system further comprises multiple internal links, such as e.g. Compact PCI—buses (Peripheral Component Interconnect, PCI), each for linking a computer unit to its corresponding interface unit.
The system further comprises a proprietary external message bus for receiving messages relayed by the interface units corresponding to the sending computer units, and for forwarding each received message to the interface units corresponding to the respective receiving computer units one received message at a time. The external message bus is linked with the interface units. The external message bus is a shared bus, i.e. only one sent message is forwarded by the bus at any given time, thus message synchronization is maintained.
However, there are significant disadvantages with the referenced prior art implementation. When more computing capacity is needed, more computer units are attached to the message bus. Thus a longer message bus is needed. Adding more computer units requires more messaging capacity between the computer units. The physical length of the message bus is limited because it is a shared bus. There is a trade-off between the length of the bus and the speed (bits per second). The higher the speed, the shorter the bus must be. The speed of the bus can be made higher by using more bits in parallel but the physical limits such as connectors and cabling will be reached very soon. Typically, the existing implementations use 8 or 16 bits in parallel.
Thus there is need for a solution overcoming the capacity limitations of the present message bus based implementations of a fault tolerant, high capacity synchronized networks.
Because the functionalities required from the system for providing message synchronism are in direct violation of present related specifications, commercially available solutions, e.g. Ethernet switches are not suitable. This stems from the fact that the specification IEEE802.1D prohibits the switch sending a message back to the same computer unit that the message was received from. Yet such a functionality is required in order to provide message synchronism in all situations. Thus current implementations, such as the one disclosed in FIG. 1, need to use proprietary components in order to achieve the desired functionalities.
Thus there is need for a solution making it possible to implement a system providing message synchronism using non-proprietary components either as-is or with only slight modifications.